Semiconductor Engineering

Tackling Chip Complexity With Integrated System-Level Test Solutions

Validate cross-chip data paths in multi-die packages and evaluate the impact on power, performance, and reliability.
Semiconductor Engineering

Smaller Geometries, Bigger Demands: The Role Of OCD In GAA Logic And Vertical Gate DRAM Process Control

AI workloads are pushing the boundaries of compute, memory, and interconnect architectures, and to meet these goals, ...
IEEE

GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning

Abstract: Automatic transistor sizing is a challenging problem in circuit design due to the large design space, complex performance tradeoffs, and fast technology advancements. Although there have ...